To reduce power dissipation in processors, logic gates of the processors are operated on minimum operating voltage (Vmin). The term “minimum operating voltage” herein refers to the minimum power supply voltage level for a process technology below which a logic gate or circuit does not operate correctly.
However, performance of sequential logic gates, such as flip-flops or latches degrades more than the performance of general combinational logic gates, such as NAND gate, NOR gates, inverters, etc. when the sequential logic gates and the general combinational logic gates are operated on Vmin power supply levels. The term “performance” herein generally refers to propagation delay of a signal from an input node to an output node of a logic gate. The term “performance” also refers to timing parameters such as setup time of a sequential logic unit. As power supply level reduces for a logic gate, the delay of the logic gate increases and so the performance of the logic gate degrades. When power supply level reduces for a sequential logic unit, setup time increases which degrades performance of the sequential logic unit.
FIG. 1 is typical flip-flop 100 with input D, output Q, and clock input CLK, which operates on a single power supply level. Flip-flops are generally placed at the boundaries of combinational logic (CL). Due to inherent contention in the data path of a flip-flop 100, the clock-to-output (CLK-Q) delay increases as power supply level reduces (e.g., at Vmin), for the flip-flop 100. Furthermore, operating the flip-flop at reduced power supply levels (e.g., at Vmin), causes the setup time of the flip-flop 100 to increase, thus degrading its performance.